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Preliminary Datasheet
R2J25953
H-Bridge Control High Speed Power Switching with Built-in Driver IC and Power MOS FET
Description
The R2J25953 multi-chip module incorporates high-side Pch MOS FET, low-side Nch MOS FET, and Bi-CMOS driver in a single HSOP-36 package. R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
Features
For Automotive application Built-in low on state resistance MOS FET. (Pch: 16 m Max., Nch: 11 m Max.) Pch MOS FET is adopted on the high-side, and the charge pump noise was lost. Built-in protection circuit of Thermal shut-down (TSD), Low Voltage Inhit (LVI), Overvoltage Detection (OVD) and Overcurrent Detection. Built-in diagnostic function. Built-in cross-conduction protection. Small Surface mounting package: HSOP-36
Block Diagram
Reverce battery protection device
VBAT Vz Cp
M
VB1
VBS1
VCC
VBS2
VB2
Pch MOS
Pch MOS
Dr.
LVI, OVD Overcurrent detection
Dr.
OUT1 TSD
OUT2
Dr.
Nch MOS
Logic
Dr.
Nch MOS
PGND1
PWM
INA
INB
DIAG
LGND
V30 C1
PGND2
Pull-up in the Microcomputer R1 power supply
Microcomputer
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Preliminary
Outline
OUT1 NC VBS1 GND V30 GND VBS2 VCC NC OUT2 NC VB1 NC VB2
19
36
TAB1
TAB3
TAB2
OUT1
1
18
NC OUT1 PWM INA INB GND LGND GND DIAG NC OUT2 NC
Pin Description
Pin No. 1 to 3 4 5 6 7 8 9 10 11 12 13 14 15 16 to 18 19 to 21 Pin name PGND1 NC OUT1 PWM INA INB GND LGND GND DIAG NC OUT2 NC PGND2 VB2 Description Power GND1 No connect Internally corrected to TAB1 PWM input A input B input Internally corrected to TAB3 IC GND Internally corrected to TAB3 Diagnostic output (open drain) No connect Internally corrected to TAB2 No connect Power GND2 MOS FET power supply 2 Pin No. 22 23 24 25 26 27 28 29 30 31 32 33 34 to 36 TAB1 TAB2 TAB3 Pin name NC OUT2 NC VCC VBS2 GND V30 GND VBS1 NC OUT1 NC VB1 OUT1 OUT2 GND Description No connect Internally corrected to TAB2 No connect IC power supply VB2 sense Internally corrected to TAB3 IC bias voltage (3.3 V) Internally corrected to TAB3 VB1 sense No connect Internally corrected to TAB1 No connect MOS FET power supply 1 MOS FET output 1 MOS FET output 2 IC tab GND
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
PGND1
PGND2
OUT2
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R2J25953
Preliminary
Absolute Maximum Ratings
(Ta = 25C)
Item Supply voltage Input voltage Diag voltage Output current Diag current Junction temperature Storage temperature Power temperature Symbol VB Vin Vdiag Iout Idiag Tj Tstg Pt Ratings 18 -0.3 to VB -0.3 to VB 50 5 -40 to +150 -55 to +150 40 Unit V V V A mA C C W Note 1 2 3 3
4
Notes: 1. 28 V at 25C, 1 min. 40 V at 25C, 1 sec. 2. Applies to INA, INB, and PWM. Clamps it with 19 V typ. 3. Applies to DIAG 4. One element operation: Tc = 25C
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Preliminary
Electrical Characteristics
(Ta = 25C, VB = VCC = 12 V)
Item Supply current VB MOS Input current Static High-side resistance Static Low-side resistance Off state current Input current High threshold Low threshold Delay time Rise time Fall time DIAG Symbol Icc0 Icc IinvbL RonH RonL Ioff IinL IinH Vthin Vtlin tpLH tpHL tr tf VDiag Min -- -- -- -- -- -- -- -- 3.0 -- -- -- -- -- -- Typ 30 3.5 -- 9 7 10 -- -- -- -- 1.5 3.0 1.0 1.0 0.4 Max 50 10 1 16 11 20 10 10 -- 1.5 4.0 6.0 3.0 3.0 0.6 10 -- -- 39.1 28.7 5.6 0.7 -- 20 1.3 1.3 Unit A mA A m m A A A V V s s s s V A C C V V V V A s V V Condition Standby ACTIVE Standby Iout = 15 A Pulse test Iout = 15 A Pulse test Vin = 0 V Vin =VB Application terminal VCC VB1/VB2 Note 1 1 1
IN
INA/INB /PWM
OUT/IN (PWM) OUT I = 2 mA, DIAG = Low Vdiag = 0 V
OUT, PWM OUT1/2 DIAG
2
Output voltage
Leak current IDiag -- -- Shut-down Tsd 150 175 temperature Hysteresis Thys 7 25 OVD Shut-down VtvH 28.9 34 voltage Return voltage VtvL 21.3 25 LVI Return voltage VRLVI 5.0 5.35 Hysteresis VHLVI 0.3 0.5 Overcurrent Shut-down IcL 35 -- detection current Detection time tcL 60 10 MOS FET Pch forward VDFp -- 1.0 Body-diode voltage Nch forward VDFn -- 1.0 voltage Notes: 1. Refer to truth table. 2. Refer to the input condition to the truth table. TSD
PWM
50%
3
VCC
VCC OUT1/2
IF = 50 A, Pulse test
50%
tpLH
tpHL
90%
90% 50% 10%
OUT1 (OUT2)
10%
50%
tr
tf
3. It is a design guaranteed value, and it doesn't apply to the final test.
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Preliminary
Truth table
The operation of OUT1, OUT2, and DIAG is shown in the following.
PWM High Input INA High Status INB LVI OVD Overcurrent detection off off off off off off off Protection circuit doesn't operate on x x x off on x x off x on x x x on TSD OUT1 High High Low Low Hi-z Hi-z Low Low Hi-z Hi-z Hi-z (Latch) Hi-z Output OUT2 High Low High Low Hi-z Low Hi-z Low Hi-z Hi-z Hi-z (Latch) Hi-z DIAG High High High High High High High High High Low Low (Latch) Low ACTIVE State
High Low Low High Low Low High High Low Low High Low Excluding All = Low At least one of PWM, INA, and INB is high.
STANDBY LVI TSD Overcurrent detection OVD
off
Notes 1. x: Regardless of High, Low, on and off. 2. Protect circuit off = undetection on = detection 3. State of pin OUT Low: Nch MOS FET ON, High: Pch MOS FET ON, Hi-z: Nch and Pch MOS FET OFF 4. The latch of overcurrent detection is released when LVI = on or INA = INB = Low.
External Parts List
Parts No. Cp R1 C1 Recommended value 10 F > 10 k 0.033 F Purpose Power supply bypass capacitor Pull up Pin DIAG Pin V30 bypass capacitor
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Preliminary
Equivalent Circuit
Pin name PGND1 PGND2 Pin No. 1, 2, 3, 16, 17, 18 Equivalent circuit
V30 OUT1 OUT2
LGND Nch MOS PGND1 PGND2
OUT1 OUT2
5, 32, TAB1 14, 23, TAB2
Pch MOS
VB1 VB2
OUT1 OUT2
Nch MOS
PGND1 PGND2
PWM INA INB
6 7 8
VCC V30
PWM INA INB
Vth Vtl to Driver
LGND
DIAG 12
DIAG
LGND
VB1 VB2
34, 35, 36 19, 20, 21
VCC
Pch MOS
VB1 VB2
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Pin name VCC LGND Pin No. 25 10 Equivalent circuit
Preliminary
VCC
LGND
VBS1 VBS2 30 26
VB1 VB2
VBS1 VBS2
VCC
V30
28
VCC
V30
LGND
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Preliminary
Main Characteristics
ICC0 vs. VCC
80 Standby Mode 8
ICC vs. VCC
Enable Mode
60
6
ICC0 (A)
ICC (mA)
40
4
20
2
0 0
4
8
12
16
0 0
4
8
12
16
VCC (V)
VCC (V)
Ron Low Side vs. Iout
12 10 VCC = 12 V 16 14 12
Ron High Side vs. Iout
VCC = 12 V
RonH (m)
RonL (m)
8 6 4 2 0 5
10 8 6 4 2
10
15
20
25
30
0 5
10
15
20
25
30
Iout (A)
Iout (A)
Turn-on Delay Time (tpLH) vs. Iout
6 5 4 3 2 1 0 0
PWM = 20 kHz, INA = High, INB = Low, VCC = 12 V
Turn-off Delay Time (tpHL) vs. Iout
6 5 4 3 2 1 0 0
PWM = 20 kHz, INA = High, INB = Low, VCC = 12 V
tpLH (s)
2
4
6
8
10
12
tpHL (s)
2
4
6
8
10
12
Iout (A)
Iout (A)
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Rise Time vs. Iout
3 2.5 2
PWM = 20 kHz, INA = High, INB = Low, VCC = 12 V
Preliminary
Fall Time vs. Iout
3 2.5 2
PWM = 20 kHz, INA = High, INB = Low, VCC = 12 V
tr (s)
1.5 1 0.5 0 0
tf (s)
2 4 6 8 10 12
1.5 1 0.5 0 0
2
4
6
8
10
12
Iout (A)
Iout (A)
ICC0 vs. Ta
45 40 35 30
VCC = 12 V, Standby Mode
ICC vs. Ta
8 7 6
VCC = 12 V, Enable Mode
ICC0 (A)
25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 150 175
ICC (mA)
5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175
Ta (C)
Ta (C)
Over-Voltage Detection vs. Ta
40 35 30 40 35 30
Over-Voltage Return vs. Ta
VtvH (V)
25 20 15 10 0 -50 -25 0
VtvL (V)
25 50 75 100 125 150 175
25 20 15 10 0 -50 -25 0
25 50 75 100 125 150 175
Ta (C)
Ta (C)
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Low-Voltage Inhibit Return vs. Ta
6 5.8 5.6 5.4 0.6 5.2 5 4.8 4.6 4.4 4.2 4 0 -50 -25 0 25 50 75 100 125 150 175 0.3 -50 -25 0
Preliminary
Low-Voltage Inhibit Hysteresis vs. Ta
0.7
VRLVI (V)
VHLVI (V)
0.5
0.4
25 50 75 100 125 150 175
Ta (C) High Level Input Voltage vs. Ta (PWM/INA/INB)
4 3.5 3 VCC = 7 V 4 3.5 3
Ta (C) Low Level Input Voltage vs. Ta (PWM/INA/INB)
VCC = 7 V
Vthin (V)
2.5 2 1.5 1 -40 -20 0 20 40 60 80 100 120140 160
Vtlin (V)
2.5 2 1.5 1 -40 -20 0 20 40 60 80 100 120140 160
Ta (C) High Level Input Voltage vs. Ta (PWM/INA/INB)
4 3.5 3 VCC = 16 V 4 3.5 3
Ta (C) Low Level Input Voltage vs. Ta (PWM/INA/INB)
VCC = 16 V
Vthin (V)
2.5 2 1.5 1 -40 -20 0 20 40 60 80 100 120140 160
Vtlin (V)
2.5 2 1.5 1 -40 -20 0 20 40 60 80 100 120140 160
Ta (C)
Ta (C)
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Ron High side vs. Ta
20 18 16 VCC = 12 V, ILoad = 15 A 16 14 12
Preliminary
Ron Low side vs. Ta
VCC = 12 V, ILoad = 15 A
RonH (m)
14
RonL (m)
Ta (C)
12 10 8 6 4 2 0 -40 -20 0 20 40 60 80 100 120140 160
10 8 6 4 2 0 -40 -20 0 20 40 60 80 100 120140 160
Ta (C)
Overcurrent Detection vs. Ta (Short to GND)
100 90 80 VCC = 12 V
Overcurrent Detection vs. Ta (Short to VB)
100 90 80 VCC = 12 V
IcL (A)
70 60 50 40 30 -40 -20 0 20 40 60 80 100 120140 160
IcL (A)
Ta (C)
70 60 50 40 30 -40 -20 0 20 40 60 80 100 120140 160
Ta (C)
Turn-on Delay Time (tpLH) vs. Ta
5
PWM = 20 kHz, INA = High, INB = Low, Io = 5 A
Turn-off Delay Time (tpHL) vs. Ta
5
PWM = 20 kHz, INA = High, INB = Low, Io = 5 A
4
4
tpLH (s)
3
tpHL (s)
Ta (C)
3
2
2
1
1
0 -40 -20 0 20 40 60 80 100 120140 160
0 -40 -20 0 20 40 60 80 100 120140 160
Ta (C)
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Rise Time vs. Ta
3 2.5 2
PWM = 20 kHz, INA = High, INB = Low, Io = 5 A
Preliminary
Fall Time vs. Ta
3 2.5 2
PWM = 20 kHz, INA = High, INB = Low, Io = 5 A
tr (s)
1.5 1 0.5 0 -40 -20 0 20 40 60 80 100 120140 160
tf (s)
1.5 1 0.5 0 -40 -20 0 20 40 60 80 100 120140 160
Ta (C)
Ta (C)
Recommended Wiring Pattern
LOAD
VB
C1 Dz
NC OUT1 NC VBS1 GND V30 GND VBS2 VCC NC OUT2 NC
VB1
TAB1 (OUT1)
VB2
TOP VIEW
PGND1 PGND2
Cp
GND
Notes 1. 2. 3. 4.
VB1 and VB2 will diverge soon because of the voltage sensing terminal and it wires for VBS1 and VBS2. GND side wiring of C1 must diverge from the LGND side. Insertion examination of use conditions about the reverse battery protection device and Dz. The reverse battery protection please choose the parts such as MOSFET or Schottky diode by use.
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
NC OUT1 PWM INA INB GND LGND GND DIAG NC OUT2 NC
TAB2 (OUT2)
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R2J25953
Preliminary
Operational Mode
When PWM is controlled, recovery control can be selected because of the low loss. However, please note that reversebrake hangs at acceleration of the motor.
Operational mode Example 1. Forward mode (Recovery control) INA = PWM on/off INB = Low PWM = High
OUT1
Circuit operational
VB1 VB2
ON OFF (Synchronizes with PWM)
Io M OUT2
OFF
OFF ON (Synchronizes with PWM)
ON
Example 2. Reverse mode (Recovery control) INA = Low INB = PWM on/off PWM = High
OFF
VB1
VB2
Io OUT1 M OUT2
ON OFF (Synchronizes with PWM)
ON
OFF ON (Synchronizes with PWM)
Example 3. Forward mode (No recovery control) INA = High INB = Low PWM = PWM on/off
VB1
VB2
ON OFF (Synchronizes with PWM)
OUT1
OFF Io M OUT2
OFF
ON
Example 4. Reverse mode (No recovery control) INA = Low INB = High PWM = PWM on/off
OFF
VB1
VB2
Io OUT1 M OUT2
ON OFF (Synchronizes with PWM)
ON
OFF
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Preliminary
Timing Chart (Normal operation)
Standby
(INA,INB,PWM = Low)
Forward (recovery) PWM
Reverce (recovery) PWM
Forward PWM
Reverce PWM
Standby
(INA, INB, PWM = Low)
INA INB
PWM OUT1 High-side VGS OUT1 Low-side VGS VB
GND VB
OUT1 GND Vf OUT2 High-side VGS OUT2 Low-side VGS VB
GND
VB OUT2 GND Vf
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Preliminary
Timing Chart (Protection operation)
Overcurrent detection INA INB (Low) OVD TSD LVI
PWM VtvH VtvL
VB IcL VHLVI
VRLVI
IOUT
tcL TSD Thys
Tj
OUT1 OUT2
Hi-z Hi-z
Hi-z Hi-z
Hi-z Hi-z
Hi-z Hi-z
DIAG
Latch cancel
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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R2J25953
Preliminary
Package Dimensions
JEITA Package Code P-HSOP36-11x14.1-0.65 RENESAS Code PRSP0036JC-A Previous Code -- MASS[Typ.] 1.96g
NOTE) 1.DIMENSION"*1"AND"*2"DO NOT INCLUDE MOLD FLASH. 2.DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
15.90.1
*1
D 19
36
12.10 2.40 2.40 0.80 0.80
Detail F
7.00.15
8.2
*2
7.5
HE
E
Reference Symbol
Dimension in Millimeters
1 e
*3
18
xM
bp
bp
S
A
b1
yS
0.20 A1
Terminal cross section
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 13.95 14.1 14.25 10.9 11.0 11.1 0.01 0.27 0.26 0.28 0.26 0 14.0 0.05 0.32 0.30 0.32 0.30 14.2 0.65 0.10 3.6 0.37 0.34 0.37 0.34 8 14.4 0.25 0.1 0.65 0.8 0.95
3.35
1.28 1.26
1.71
c1 c
Ordering Information
Part No. R2J25953-00 Quantity 700 pcs/ box Shipping Container Tray
R07DS0044EJ0300 Rev.3.00 Sep 01, 2010
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Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 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